路由程序

基本解释 (translations)

router

与路由程序相关的网络例句 [注：此内容来源于网络，仅供参考]

FlyWay - FlyWay is a navigational route planner for pilots.

FlyWay是一个用于飞行员的导航路由计划程序。

This invention relates to a DC linear motor digital controller including a central processor circuit, a data memory, a program memory, an A/D conversion circuit, a D/A conversion circuit, a linear shift orthogonal code pulse signal circuit, a signal isolation circuit, among which, the center processor circuit is composed of a special DSP chip controlled by the motor, a complicated programmable logic device CPLD combining with a peripheral expanding circuit, said digital controller fully utilizes the motor to control the special DSP chip to integral DSP kernel CZXLP and the rich external circuit in a single chip to make up of a digital controller for controlling high frequency response DC linear motor with small volume, low dissipation and high reliability.

高频响直流直线电机数字控制器，属于电机自动控制技术领域，目的在于获得快速、高精度往返运动的控制效果，实现高频响直流直线电机的精密位置跟踪控制功能。本发明包括中央处理器电路，数据存储器，程序存储器，A/D转换电路，D/A转换电路，直线位移正交编码脉冲信号电路，信号隔离电路；中央处理器电路由一个电机控制专用DSP芯片，复杂可编程逻辑器件CPLD，结合外围扩展电路组成。该数字控制器充分利用电机控制专用DSP芯片将高性能DSP核C2xLP和丰富的功能外设电路集成在单个芯片上这一特点，构成了一个体积小、功耗低、可靠性高和功能比较齐全的高频响直流直线电机控制用的数字控制器，使系统的整体成本大大降低。

This dissertation introduces the whole scheme、the hardware electro circuit design and software design, the result of experiment on salinometer is preferred at the end of the dissertation. Salinometer is base on SOPC technology, and use digital technology to design circuit: the excitation source for balance bridge is generated by digital method, its shape、amplitude and frequency can be control by digital signal, the standard branch of bridge is composed of three digital-analog-conversion, and uses the method of successive approximation to regulate the balance of bridge.

盐度计以SOPC技术为基础，通过数字化方式设计测量电路：电桥的激励源由数字化方式产生，激励源的波形、幅值和频率等可由数字量控制；平衡电桥标准支路由3个数模转换器组合实现，测量时以逐次逼近的方式调整电桥的平衡度；检测电桥平衡度的高灵敏度数字检流计同样以数字化方式设计，它的增益由程序控制，将电桥的输出电压数字化，以软件判断电桥平衡度。

The analysis of the optical signal transmission characteristics and the physical parameters provides the theoretical foundation for optimizing the design and improving the performance of AWG; and the optimizing design numerical value calculation method solves the complex problem of the optimizing design of the AWG, it can also provide a way for AWG computer aided design system; the AWG optical signal processing analysis provide a way for optical signal Fourier transform, serial and parallel transmission, circle shift, matrix transform and differential processing; the optical signal processing characteristics of AWG develop AWG to use for new field, and the optical signal processing will play an important role on all-optical networks in the future; by the definition of the wavelength transform matrix of the AWG, the signal output positions that come from these input signals of the different wavelength or the same wavelength but the different input ports and carrying different signals can be accurately determined, and the wavelength transmission matrix plays an important role for analyzing the routing of the complex optical network, or designing the network nodes such as the optical path add/drop multiplexer and optical cross connect device; the wavelength transmission matrix also provides a method for monitoring and managing the wavelength transmission of the optical network nodes; e analysis of the AWG' OXC node structure and wavelength routing provides a way for realizing the OXC, especially for multi-path/multi-wavelength OXC and the intelligence node of the optical networks; by the studying of the control plain characteristics, router, traffic engineering, program and the improved arithmetic of the wavelength routing, the method for realizing the GMPLS' OXC optical transport network is provided, and it play an important role for the study of the automatic switched optical network; the time-frequency analysis can provide more information about the dispersion and energy changes of .the pulsed light transmission in the singlemode fiber, it also provides more useful parameters for analyzing the dispersive accumulating and dispersive compensating.

AWG光信号传输特性与相关参数的分析，为进一步优化设计AWG及提高其性能提供了理论依据，而优化设计计算数值方法解决了AWG优化设计计算的复杂问题，为进一步建立AWG的计算机设计系统提供了基础；AWG光信号处理的特性分析，提出了AWG应用的新领域，为光信号的傅立叶变换、串并传输、循环移位、矩阵变换、微分处理等提供了一条途径；波长传输矩阵变换关系的建立，不仅得到了确定多路AWG每路信号从输入端口到输出端口的准确输出位置的方法，而且在分析应用AWG实现复杂的光通信网络路由的连接、特别在设计分插复用器和交叉连接器等网络节点时有重要的作用，能有效而准确地确定波长的路由关系，为实现节点波长传输路由的监控和管理提供有效手段；基于AWG的OXC结构和波长路由的确定为实现OXC技术、特别是多路多波长的OXC和光网络的智能节点技术提供了有效的方法；控制平面的特征、路由器、流量工程、程序及改进的波长路由算法的研究实现了基于GMPLS的OXC光传送网络的控制平面，为建立自动交换光网路提供了一定的基础；时频分析可以更直观和更清晰地描述脉冲信号在单模光纤中传输色散和能量的变化，为色散积累和色散补偿提供有效的分析参数。

The authors emphatically research that how to utilize the intermediate driver in network driver interface specification to realize the architecture of software platform for wireless ad hoc network in power system; present Passthru based frame of program, optimized link state routing protocol and the principle to implement modules of the program; discuss the feature of the network platform and look forward to the application prospect of the network platform.

针对无线网在电力系统中广阔的应用前景，进一步研究了无线自组网在电力系统中的应用，重点讨论了如何利用NDIS(network driver interface specification)中间驱动程序实现电力系统中的无线自组网软件平台架构，介绍了基于Passthru的程序框架、最优化链路状态路由协议及程序模块的实现原理，并讨论了网络平台的特性，展望了其应用前景。

Another problem is automatically seeking the route . Former model is complexity, so we put forward the method of predigestion, and set up a model of dendriform network.

自动路由的查找是本工程中的一个难点，在考虑到原来的模型比较复杂的情况下，根据实际情况，提出了简化模型的方法，建立了一个树型的设备模型，在此基础上，在程序中实现了自动路由的查找。

SwitchSniffer is a program that can scan your switched LAN for up hosts and can reroute and collect all packets without the target users' recognition.

switchsniffer是一种程序，可以扫描您的开关兰最多的主机和可以重新路由，并收集所有的数据包，没有目标用户的认同。

In the chapter 4, we discuss the routing program, which is the core of the whole system.

第四章，讨论了整个系统的核心，也就是路由程序。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

与路由程序相关的网络解释 [注：此内容来源于网络，仅供参考]

Diversely Routed Automatic Protection Switching：下同路由自动自动保护切换

Defense Advanced Projects Research Agency 美国国防高级计划研究署 | Diversely Routed Automatic Protection Switching 下同路由自动自动保护切换 | Damage Assessment Routine 故障评定例行程序逻辑

initiate：启动

指不论在本条生效之前或之后--"手稿程式"(scripts) 指对资讯系统作出的一列指示或指令;"登记"(register) 就电邮地址而言,指--"例行传递"(routine conveyance) 指透过自动化的技术程序传送、路由、转发、处理"启动"(initiate) 就商业电子讯息而言,

internal division：内部分割

subnetting 子网划分 | internal division 内部分割 | routing daemon 路由后台程序

main line：主线

它从总线上接收数据后传送给应用程序,或是把应用程序数据传给其它设备. 每个EIB设备通过LC(Line Connector,具有路由功能)连接到主线(Main Line)上,BC(Bus Coupling)向特定应用的硬件(如传感器和作动器)提供了定义良

Mathematical Programming System：数学程序系统

Multi-Protocol Routing 多协议路由选择 | Mathematical Programming System 数学程序系统 | Microprocessor System 微处理器系统

patching error：修补程序错误

patching a program 修补程序 | patching error 修补程序错误 | path 路由

PICS ProtocolInformationConformanceStatement：协议信息一致性说明

PIN 协议独立型多目标广播-稀疏型(路由协议) | PICS ProtocolInformationConformanceStatement 协议信息一致性说明 | PI ProtocolInterpreter 协议解释程序

TDRTime Domain Reflectometry：时域反射

8TDPRTrace Directed Program Restructuring痕迹导向的程序重构 | 9TDRTime Domain Reflectometry时域反射 | 10TDRTime of Day Routing日期路由选择

Routing Information Protocol RIP：路由信息协议

这个度量用于路由信息协议(routing information protocol rip)为网络建立选路表. [8] ifconfig所用的缺省的度量值是零. 如果你没有运行一个rip后台程序,你一点也不需要这个选项;如果你用了,你也很少需要改变度量的值. 这个接口是一个回送(loopback)接口.

Restructured Extended Executor：扩充重结构化执行程序语言

Route Extension 路由扩展 | Restructured Extended Executor 扩充重结构化执行程序语言 | Radio Frequency 射频