端相

词组短语

look sb. up and down

与端相相关的网络例句 [注：此内容来源于网络，仅供参考]

A frequency divider, comprises: an inverting unit comprising an input, and an output; and a plurality of switch inverters in series, having at least a first switch inverter and a last switch inverter; each switch inverter comprising two inphase switches, in which the first switch inverter is connected to the output of the inverting unit, and the last switch inverter is connected to the input of the inverting unit; wherein the two inphase switches of each of the switch inverters are respectively supplied by a first voltage and a second voltage, any two of the adjacent switch inverters are respectively controlled by two inverted clocks, thereby the two inphase switches are selectively turned on synchronously and turned off synchronously.

反相单元包含输入端以及输出端；串联的多个切换反相器，具有至少一第一切换反相器以及最终切换反相器，每一切换反相器包含两个同相开关，其中第一切换反相器连接于反相单元的输出端，且最终切换反相器连接于反相单元的输入端；每一切换反相器的同相开关分别由第一电压与第二电压供电，任何两个相邻的切换反相器分别受控于两个反相时钟，因此该两个同相开关是选择性同步开启及同步关闭的。

In high-impedance current-input inverting configurations, where a length of shielded wire is used to guard the lead from the current source to the amplifier's inverting input, the guard should either be driven by a buffer at the same potential as the non-inverting input, or be tied directly to the non-inverting input, with a second outer shield connected to the signal's reference point.

如果将运放接成反相放大器的形式，并且在信号源与运放反相端之间用一段带有屏蔽层的导线来充当的防护罩，那么对防护罩的处理有两种选择：要么用一个缓冲跟随器来驱动，跟随器输出端与运放同相端电位相等，而且除跟随器外，防护罩不与其他点接触；要么将防护罩直接接到运放的同相端，然后在其外面加一个屏蔽层，并且将屏蔽层连接到信号的参考电位。

The invention discloses a DC/DC circuit, comprising a PWM controller, a current amplifier, a peak current comparator, an error amplifier, a main switch, a synchronous switch and also an operational amplifier. The non inverting input end of the operational amplifier is used for coupling with input voltage or voltage reference, or used for coupling with the input voltage and the voltage reference; the inverting input end of the operational amplifier is used for coupling with the voltage reference or ground, and the output end thereof is connected with the non inverting input end of the error amplifier.

本发明公开了一种DC/DC电路，包括PWM控制器、电流放大器、峰值电流比较器、误差放大器、主开关和同步开关；还增设运算放大器，其同相输入端用于与输入电压或基准电压耦合，或用于同时与输入电压和基准电压耦合；其反相输入端用于与基准电压或地耦合，其输出端与所述误差放大器的同相输入端连接。

S1 is then changed to position 1. The voltage stored on C1 is inserted between the output and inverting input of the amplifier and the output of the amplifier changes by VIN to maintain the amplifier input at the input offset voltage. The output then changes from (VOS + IbiasR2) to (VIN + IbiasR2) as S1 is changed from position 2 to position 1. Amplifier bias current is supplied through R2 from the output of the amplifier or from C2 when S1 is in position 2 and position 1 respectively. R3 serves to reduce the offset at the amplifier output if the amplifier must have maximum linear range or if it is desired to DC couple the amplifier.

接着 S1 拨到位置 1，使 C1 的电压加在放大器的输出端和反相输入端之间，(由于电容端电压不能突变，所以)输出端的电压将产生大小等于 VIN 的变化，使放大器输入端维持输入失调电压，即当开关 S1 从位置 2 拨到位置 1 时，输出端电压将从(VOS + IbiasR2)变为(VIN + IbiasR2)。S1 处于位置 2 时，放大器的偏置电流是由输出端经电阻 R2 提供的，当 S1 转向位置 1 时则由 C2 提供。R3 的作用是降低输出失调电压，如果要求放大器具有最大的线性范围，或者采用直流耦合，就应该使用该电容。

After being connected with a resistor in series, the primary input end of a transformer is connected with the output end of the live wire and the output end of the null line in parallel, the secondary output end is connected with the two ends of the earth wire switch in parallel after being connected with another resistor in series, one end of a neon lamp in a photoelectric coupler is connected with the input end of the earth wire E and a secondary end of the transformer, the other end of the neon lamp is connected with the centers of the two resistors, one end of a light sensitive resistor in a photoelectric coupling switch is connected with the anode of an integrated circuit power in the creepage protector, the other end of the light sensitive resistor is connected with the anode of a diode, the cathode of the diode is connected with the triggering pole of the silicon-controlled rectifier in the creepage protector, the neon lamp and the light sensitive resistor are positioned into a dark box, and a small hole which avoids the light sensitive resistor is formed on the dark box.

防止地线触点未导通的全能安全插头，包括各带开关的地、零、相三线接线和由零序互感器、脱扣器、放大器、整流器、试验回路和可控硅组成的漏电保护器，变压器初级输入端串联电阻后并接在火线输出端和零线输出端，次级输出端与电阻串联后并联在地线开关两端，光耦内氖灯的一端与地线E输入端和变压器次级的一端连接，氖灯另一端与二电阻的中心连接，光电耦合开关内光敏电阻的一端与漏电保护器内的集成电路电源正极连接、光敏电阻的另一端与二极管的正极连接，二极管的负极与漏电保护器内的可控硅触发极连接，氖灯和光敏电阻置于暗箱中，暗箱上开一避开光敏电阻的小孔。

The electric connector is characterized in that the male connector also comprises an insulation sheath arranged at the end of the wire and on the periphery of the male terminals, correspondingly, the female connector also comprises an insulation sheath arranged at the end of the wire and on the periphery of the female terminals, and the insulation sheath in the male connector is mutually matched with the insulation sheath in the female connector and can be inserted into the insulation sheath in the female connector.

一种电连接器，包括有公插和母插，该公插包括两个分别与电线的两极相电连接的呈棒状的公端子，该母插包括两个分别与电线的两极相电连接的呈圆筒状的母端子，所述公端子与母端子相配而可相互插配一起，其特征在于所述公插还包括设置在电线端部和公端子外围的绝缘护套，对应地，所述母插包括设置在电线端部和母端子外围的绝缘护套，并且，所述公插中的绝缘护套与所述母插中的绝缘护套相匹配而可插入到该母插中的绝缘护套之内。

This finding is emphasized in a press release from Novartis, which states that there were 30% fewer distant recurrences with letrozole than with tamoxifen (87 vs 125 patients) and then explains that distant recurrences increase the likelihood of death from the disease."Avoiding distant metastases in early breast cancer is very important, because we know that this type of recurrence significantly worsens the prognosis for these women," Dr Mauriac is quoted as saying. Letrozole "may be beneficial in reducing early relapse," he adds.

在一项来自诺华药厂的新闻稿中强调这项发现，他们宣称使用letrozole相较於tamoxifen，发生远端转移的机率下降了30%（87位相较於125位病患），且接著解释远端再发会增加死於这个疾病的可能性；避免远端再发对早期乳癌来说是非常重要的，因为我们知道这种形式的再发显著地恶化这些妇女的预后；他附带表示，letrozole在降低早期再发上可能是具有好处的。

Secondly, there are the clusters with clear 7 fold symmetry and transformation point at lower temperature in liquid metals.

二是发现液态金属中存在着明显的7度对称性原子团和低温端相变点。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

与端相相关的网络解释 [注：此内容来源于网络，仅供参考]

antiparallel：反向平行

虽然DNA分子的两条链互补,但方向不同,是互为反向平行(antiparallel)的,一条链的5-端与互补链的3-端相对应,反之亦然. 所以,若一条链的碱基序列是5-ATGCGCTGA-3',则另一条链将是3-TACGCGACT-5'. 细胞内大多数涉及DNA的反应过程都沿5-端到3-端进行的,

broadside array：垂射天线阵,端射天线阵,多列同相天线阵

broadside | 宽边,宽面 | broadside array | 垂射天线阵,端射天线阵,多列同相天线阵 | broadwise | 横向,沿宽度方向

inverting input terminal：反相输入端

反相放大器 inverting amplifier | 反相输入端 inverting input terminal | 非常态网络 improper network

INV invertor：倒相器,翻转器,反相器,变换器

INP input 输入(端口) | INV invertor 倒相器,翻转器,反相器,变换器 | Inverse 倒相

INV invertor：倒相器,反相器,变换器

INP input 输入(端口) | INV invertor 倒相器,反相器,变换器 | Inverse 倒相

non-inverting input terminal：同相输入端

同相 in phase | 同相输入端 non-inverting input terminal | 凸电阻元件 convex resistor

extreme relativism：極端相對論

extreme ordering 外加的次序 | extreme relativism 極端相對論 | extreme universalism 極端普遍論

extreme universalism：極端普遍論

extreme relativism 極端相對論 | extreme universalism 極端普遍論 | extrusion 排出;復現

interspersing：(相邻相端线圈的)交替连接

intersperse in time || (按)时间散布 | interspersing || (相邻相端线圈的)交替连接 | interspherulite boundary strength || 球晶界(面)间强度

Inverting：反相

将运算放大器的反向输入端与输出端连接起来,放大器电路就处在负反馈组态的状况,此时通常可以将电路简单地称为闭环放大器. 闭环放大器依据输入讯号进入放大器的端点,又可分为反相(inverting)放大器与非反相(non-inverting)放大器两种.