流水线结构

词组短语

pipeline organization · pipeline architecture

与流水线结构相关的网络例句 [注：此内容来源于网络，仅供参考]

In order to reduce the quantization error of pipelined A/D converter, a simple and efficient modified algorithm is presented.

为了减小流水线结构A/D转换器的量化误差，提出了一种简单有效的改进算法。

This invention discloses a multi-queue sequence buffer management circuit and a method based on a pipeline applying a pipeline structure including: an arbitration circuit selecting one for process from read, write and distribution buffer requests, a buffer slot state module designing state of the slot requiring operation and queue numbers and assigning idle slots, a buffer slot filter module filtering the slot, a buffer slot filter module filtering the slot states not belonging to the current operation queues nor idle aligned in terms of the head pointer, a queue slot selection module computing continuous idle slot numbers from the slot pointed by the head pointer and refreshing the head pointer and selecting preparing slots, a queue slot prior queuing module refreshing the read pointer and result numbers of the current operation queues with the pointer of the first prepare slots and their numbers which can support multi-queue to share one buffer space, queues can access the buffer in overlap.

本发明公开一种基于流水线的多队列顺序化缓冲管理电路及方法，本发明电路采用流水线结构，包括：仲裁电路，从读、写、分配缓冲请求中选取一路进行处理；缓冲槽口状态设置模块，设置请求操作的槽口状态和队列号，分配空闲槽口；缓冲槽口滤除模块，滤除不属于当前操作队列且非空闲态的槽口状态，按头指针对齐；队列槽口选择模块，计算头指针指向槽口起的连续空闲槽口数并更新头指针，选出预备态的槽口；队列槽口优先排队模块，用第一个预备态槽口的指针和预备态槽口数分别更新当前操作队列的读指针和结果数；本发明可以支持多个队列共享一个缓冲空间，各类指令队列能对缓冲进行交叉访问，并对指令结果的写入读出进行顺序化管理。

AT FIRST THIS PAPER DESCRIBES THE PIPELINE STRUCTURE, INSTRUCTION SET, INSTRUCTION CODE, AND PIPELINE HAZARD.

阐述了MIPS五级整数流水线结构相应的指令功能及编码，以及流水线竞争中结构竞争数据相关等问题。

It's much easier to implement the scalable FFT processor based on multilevel pipeline processing architecture.

特别是流水线结构使得FFT处理器在进行不同点数的FFT计算时可以通过对模块级数的控制很容易的实现。

The real-time compution of FFT with high-speed and large capacity of data flow can be realized by parallel data processing or multilevel pipeline processing.

面向高速、大容量数据流的FFT实时处理，可以通过数据并行处理或者采用多级流水线结构来实现。

Pipeline ADC; System level model; Sample and Hold Circuit; MDAC; Digital Correction; Operational Amplifier

流水线结构；系统级模型；采样保持电路； MDAC；数字校正；运算放大器

During the design of VXI-bus Serial Controller Module, the functions of VXI-bus including time-sequence for VXI interface, resource management, interrupt process, bus arbitration, are accomplished. To advance the performance and stability, the FPGA technic is used to implement the kerneled code including serial bus time-sequence switching to VXI interface time-sequence, the UART, the Parameterized Baud Generator and"Pipeling frame". The handle type of Data Transfer Bus for VXI-bus is researched thoroughly, and the format of serial data transfer is designed.

在VXI总线串行控制器设计中，实现了VXI总线控制器的基本功能，包括VXI总线接口时序、总线仲裁、超时处理等；同时利用先进的FPGA技术实现了串行总线时序向VXI总线时序的转换、通用异步收发器、参数化波特率发生器、流水线结构等功能模块；在设计中还深入研究了VXI总线数据传输的各种操作类型，制定了串行数据传输的编码格式。

The pipelined implementation shows that the new algorithm occupies about 1/16 of the old one.

采用流水线结构的硬件实现表明，新算法占用的资源大约为原来的1/16。

In the experiment,simulators for PISA and StrongARM are generated,and some research on design space exploration about application of encryption and decryption based on this platform is made,thus to demonstrate the retargetability and validity of the environment.

实验部分完成了PISA和StrongARM两种体系结构的周期级模拟，并进行了针对加解密应用的流水线结构设计空间搜索的研究，证明了该环境的可重定向性和有效性。

The pipelined CORDIC architecture is very suitable for FFT butterfly operation because of its high throughput and regularity, but it will consume lots of resources,this article presents an improved architecture of CORDIC pipeline,starting with the property that the FFT rotary factor is fixed but not arbitrary,and according to the mapping between the basic rotational angle of CORDIC and scale factor and the rule for transform among the scale factors.On the condition that the velocity of FFT butterfly operati...

CORDIC流水线结构因其高吞吐率及规整性，而很适合于FFT蝶形运算，但其缺点是耗资源多，本文从FFT中旋转因子固定不任意的特点出发，根据CORDIC基本旋转角度与缩放因子的对应关系和缩放因子之间的转换规律，对CORDIC流水线结构进行了改进，在蝶形运算速度不变的情况下，进一步减少所耗资源，在字长为16位的FFT中，每个旋转因子可用25位的控制序列来替代，从而使每个旋转因子的存储空间由32位减少到25位。

与流水线结构相关的网络解释 [注：此内容来源于网络，仅供参考]

DEC：(译码 )

对应的流水线结构分别为:取指(Ifet ch)、译码(Dec)、执行(Exec)、存储器操作(Mem)和写回寄存器(WB). 如图2所示,指令在流水线上顺序执行,但是同周期有五条指令相交迭. 所以采用流水线结构大大提高了指令的并行性,CPI近似等于1.

instruction decode：指令译码

[文摘]:该课题所设计的微处理器共包括两部分:整数单元和浮点单元.整数单元采用五级流水线结构分别为指令提取(Instruction Fetch)级、指令译码(Instruction Decode)级、指令执行(Execution)级、存储器访问(Memory access)级、写回(Write Back)级.论文详细阐述了流水线设计过程,

dilation：膨胀

布尔处理对形态学(Morphology)运算尤其有用,例如,膨胀(Dilation),扩展(Expansion)以及收缩(Shrinking). 图3.24 流水线结构的图像处理机(PIPE)结构方框图(点击查看大图)(2)输入级(Input Stage)和输出级(Output Stage)ISMAP既位于流水线上,

pipeline organization：流水线结构

pipeline operation 流水线操作,流水线运算 | pipeline organization 流水线结构 | pipeline positioning 管道定位

submarine pipeline：海底管线

流水线结构:under pipeline | 海底管线:submarine pipeline | 油气管道:Oil Gas Pipeline

pipelining：流水线操作

它的关键技术在于采用 流水线操作(Pipelining),和等长指令体系结构,使一条指令可以在一个单独操作中完成, 从而实现在一个时钟周期里完成一条或多条指令.同时 RISC 体系还采用了通用快速寄存器 组的结构,大量使用寄存器之间的操作,

superscalar：超标量体系结构

苹果公司与IBM公司针对PowerPC 970超标量体系结构(Superscalar)、超级流水线结构(Superpipelined)的执行内核,在其设计中增加了"极速引擎"(Velocity Engine),具备了创新的数据处理性能,能够优化数据和指令流.

superscalar architecture：超标量结构

外围计算机 peripheral computer | 超标量结构 superscalar architecture | 超流水线结构 superpipelined architecture

pipelined ADC：流水线模数转换器

介绍了一种适用于10位80MS/s流水线模数转换器(Pipelined ADC)的采样/保持(S/H)电路.该电路为开关电容结构,以0.25μm CMOS工艺实现.采用栅源电压恒定的栅压自举开关和底极板采样技术,极大地减小了采样的非线性失真.基于该S/H电路的流水线A/D转换器在80MHz采样率下,

streamlining：流水线

1,最原始业务的过程重塑,它是使用信息技术(IT),重新设计和调整操作过程流水线(streamlining)从而提高运作效率,从而获得竞争优势. 2,对组织结构进行改造、提高. 它是一种通过改造跨功能业务过程,优化组织结构,人力资源及信息技术等以改善企业业绩效的策略.