- 更多网络例句与时钟脉冲周期相关的网络例句 [注：此内容来源于网络，仅供参考]
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Because each clock cycle has both a high and a low state, after the first clock pulse, two LEDs will always be on—that is, LED 1, LED 1 and 2, LED 2 and 3, LED 3 and 4, and so on.
因为每个时钟周期都是高低电平状态，第一个时钟脉冲后，两个LED通常是亮的——也就是说，LED1，LED1和2，LED2和3，LED3和4，等等。
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The two elementary working courses of phaselock loop, locking and tracing, are dissected,and the tracing condition is applied to the on the spot diagnosis of malfunctional gears in a gearbox .
将该技术的跟踪工作状态运用于齿轮箱故障诊断，在锁相环路输出信号的一个周期内发出一定数量的脉冲作为时域平均处理的外采样时钟，消除了转速不均的影响。
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The invention relates to a method for synchronizing at least one node of a bus system, which is operated with a predeterminable system clock period, whereby a local clock period and a reference clock period are given for the at least one node, and the reference clock period is synchronized with the system clock period. A local clock period, which is synchronized with the system clock period, of the at least one node is produced whereby linking the local clock period with a splitting factor, whereby the splitting factor represents a ratio of the reference clock period to the local clock period. The splitting factor for synchronizing the local clock period with the system clock period is adapted by adding or subtracting a adaptation value.
用于同步至少一个总线用户的方法，所述的总线系统用可预定的系统周期运行，由此为该至少一个用户给定局域时钟脉冲周期和基准时钟脉冲周期并且把局域时钟脉冲周期与系统时钟脉冲周期同步，其中通过把局域时钟脉冲周期与分配系数相关联的方式产生同步到系统时钟脉冲周期的、至少一个用户的局域时钟脉冲周期，其中，分配系数说明基准时钟脉冲周期与局域时钟脉冲周期的比例，其特征在于，通过加或者减一个适配值或者说补偿值，对用于把局域时钟脉冲周期与系统周期同步的分配系数进行匹配。
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But errors lies in the way of counter lead the bad measurement, especially when it needs high precision or the clock pulse is wider than the difference.
但是由于计数方法本身的误差，在测量精度要求比较高或是在鉴相脉宽小于用于计数的时钟脉冲周期时，原来的测量方法就无法满足实际的测量要求。
- 更多网络解释与时钟脉冲周期相关的网络解释 [注：此内容来源于网络，仅供参考]
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clock cycle：时钟周期
(1)时钟周期(clock cycle)的频率:8253/8254PIT的本质就是对由晶体振荡器产生的时钟周期进行计数,晶体振荡器在1秒时间内产生的时钟脉冲个数就是时钟周期的频率.
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clock cycle：脉冲周期
到达接收端的时间不同步,时钟脉冲相位差降低了信号沿到达的可预测性,如果时钟脉冲相位差太大,会在接收端产生错误的信号,如图1所示.传输线时延已经成为时钟脉冲周期(Clock Cycle)中的重要部分.
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clock cycle：时钟(脉冲)周期
时钟脉冲相位差是指同时产生的两个时钟信号,到达接收端的时间不同步. 时钟脉冲相位差降低了信号沿到达的可预测性,如果时钟脉冲相位差太大,会在接收端产生错误的信号,如图l所示. 传输线时延已经成为时钟脉冲周期(Clock Cycle)中的重要部分.
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clock cycle：同步脉冲周期
climatic pessimum气候恶劣期 | clock cycle同步脉冲周期 | clock period时钟周期
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half clasping：半抱茎的
half chronometer 半精密记时表 | half clasping 半抱茎的 | half clock period 半时钟脉冲周期