数据通信线路

词组短语

tie line

与数据通信线路相关的网络例句 [注：此内容来源于网络，仅供参考]

The defining charactenstics of LANs.in contrast to WANs,include their much higher data transfer rates,smaller geographic range,and lack of a need for leased telecommunication lines.

与WAN相比，LAN的标志性特征有：数据传输率更高、覆盖的地域较小、无需租用远程通信线路。

So data communication through power line need not to impropriate wireless channel resources and pave definite-purpose communication line. It also can take full advantage of electric facilities and exert power resources.

利用它进行数据通信，传递各种信息，不占用无线频道资源，亦无需铺设专用通信线路，省工、省钱、维护简单，从而能够充分利用电力设施，发挥电力资源优势，发展电力通信产业。

After lucubrating the problem of data transfer velocity matching, buffer technology that is used to solve the problem is presented and all the parameters of the technology are given.

根据此系统的功能模型和数据传输线路规程，详细分析了DNC通信平台、事件接收平台和DNC控制器内核的实现方法。

The TW-770 frequency will not disturb voice, data-communication lines, or electrical service when the coupling clamp is used.

这个TW- 7700的频率，不会打扰语音，数据通信线路，电器维修等，当耦合钳用。

There is provided a data communication technique capable of flexibly assuring a band for a traffic generated and effectively using the access line or radio resource.

本发明提供能够对发生的通信量灵活地确保频带，又可以有效利用接入线路或无线资源的数据通信的技术。

Should quoting errors occur, which may include, but are not limited to, a mistype of a quote by CMS, a quote which is not representative of fair market prices, an erroneous price quote from a CMS employee, such as but not limited to a wrong big figure quote or an erroneous quote due to failure of hardware, software or communication lines or systems and/or inaccurate external data feeds provided by third-party vendors, CMS will not be liable for the resulting errors in account balances.

报价错误：如果出现报价错误，这些错误包括但不限于：由于CMS打字错误而产生的报价错误，不代表公平市场价的报价，CMS员工的错误报价，例如但不限于，错误的大数字报价或由于硬件、软件、通信线路或系统之故障产生的错误报告，以及第三方供应商提供的外部数据，CMS不应为由此而在帐户余额上产生的错误而承担责任。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

The distributed fusion algorithm was applied to process the fusion tracks from local ATC center,and solve the problem of the poor quality of the track on the fusion edge.

为实现全国范围内的空中交通动态监视，必须将分布于全国各地的管制中心的雷达融合数据经通信线路传送到全国空情融合中心，常用的办法是进行动态雷达数据拼接，在拼接边界存在航迹平滑度差，航迹易跳变等问题。

Data to support these applications are sent to the mainframe from the store minicomputers over communication lines.

支持这些应用的数据是各分店里的小型计算机通过通信线路送给主机的。

与数据通信线路相关的网络解释 [注：此内容来源于网络，仅供参考]

bandwidth：带宽

"带宽"(bandwidth)有以下两种不同的意义:1.指信号具有的频带宽度.信号的带宽是指该信号所包含的各种不同频率成分所占据的频率范围.2.在计算机网络中,带宽用来表示网络的通信线路所能传送数据的能力,

DCC DigitalCodeConverter：数字代码转换器

7 DCC DataCircuitConcentrator 数据线路集线器 | 8 DCC DigitalCodeConverter 数字代码转换器 | 9 DCC DigitalCellularCommunication 数字蜂窝通信

dedicated line：专线

参见加密(encry Ption) 专线(dedicated line) 为数据传输保留的专用通信线路,它不是在传输时才进行交换连接的线路. 参见租用专线(leased line). 默认路由(default route) 该路由条目是用来为其下一跳地址没有被显式地列在路由选择表中的数据帧进行导向的.

PVC：永久虚电路

基本业务功能:包括"交换虚电路"(SVC)和"永久虚电路"(PVC)两个子类. [说明]在X.25分组交换网中,它的通信传输线路分为分组交换机(PSE)间的"中继传输线路"和"用户传输线路"两类. 中继传输线路通常使用n×64Kb/s的数字数据信道,

SVC：交换虚电路

基本业务功能:包括"交换虚电路"(SVC)和"永久虚电路"(PVC)两个子类. [说明]在X.25分组交换网中,它的通信传输线路分为分组交换机(PSE)间的"中继传输线路"和"用户传输线路"两类. 中继传输线路通常使用n×64Kb/s的数字数据信道,

circuit switching：线路交换

在电脑网络理论中,通常把这种将数据从线路的一端直接传送到另一端的方式称为"线 路交换"(Circuit Switching). 而这种由强大的网络服务器管理的网络则通常被称为中 央控制式网络(Centralized Networks). 我们平常理解的电子通信也都是这样:在一个中央控制的系统之中,