- 更多网络例句与数字行相关的网络例句 [注：此内容来源于网络，仅供参考]
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A digital video cassette recorder 4-1 connected to the IEEE1394 high-speed serial bus 11-1 extracts digital video data through the processes opposite to those carried out in the transmitter side.
与IEEE1394高速串行总线（11―1）连接的数字录像机（4―1），进行与发送侧相反的处理，并提取数字视频数据。
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The experiment shows that,there is phase drift of low frequency in the digital image seriel acquired by CCD camera and frame grabber,different CCD has different drift characteristic and level;the phase drifts are not identical even in the same image line,the phase drift of neighboring locations in an image line has distinct correlation;the drift levels ...
实验表明：经 CCD Camera和图像卡采集的数字图像序列中存在着低频的图像抖动，即位相漂移。而且不同的 CCD Camera具有不同的漂移特点和程度，甚至在同一个图像行内的漂移也不完全一致。一般在图像行内相近的位置之间，位相漂移有明显的相关性，不同的图像行之间的漂移的程度相同，但没有相关性。最后本文还给出了一种位相漂移的修正方法
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Moreover, other peripheral in communication with the ICH 38 may include, in various embodiments of the invention, integrated drive electronics or small computer system interfaces hard drive, USB ports, a keyboard, a mouse, parallel port, serial port, poppy disk drive, digital output support e.g., digital video interface (DVI, or the like.
此外，与ICH38通信的其他外围在本发明的各实施例中可以包括集成驱动器电子电路或小型计算机系统接口硬盘、USB端口、键盘、鼠标、并行端口、串行端口、软盘驱动器、数字输出支持例如，数字视频接口
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The child could be asked to point to different numbers and to describe their relationship to other numbers on the line.
孩子会被要求指出不同的数字，并描述与这行中其他数字之间的关系。
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At the begining of the game,numbles have been filled in some grids in the gridiron pattern,player should fill the blank grids with numbers 1 to 9,and make sure that they're non-repeated in every row,column and Gong,besides,the answer is unique in one round.
游戏刚开始时，盘面上有些小格已经填了数字，游戏者要在空白的小格中填入1到9的数字，使得最后每行、每列、每宫都不出现重复的数字，而且每一个游戏都只有一个唯一的解答
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Firstly, the digital watermarking was transformed randomly, and then encrypted by chaos. The encrypted watermarking was transformed to one-dimensional row vector, and the pixel value was sorted. The coefficient of primitive image of stationary wavelet transformation was expanded to one-dimensional row vector, too, and then the sorted watermarking was embedded to the sorted low frequency and turned to two dimensions.
本算法先将数字水印图像进行置乱变换，然后将置乱后的水印图像进行混沌加密，将加密后的水印按行展开成一维行向量，并将像素值从大到小排序，将原始图像平稳小波分解得到的低频系数也按行展开成一维行向量，并按从大到小排序。
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The design of the modern electronic device, except for must has multiple functions, but it also trend to achieve slightness, thinness, shortness and smallness in outer appearance. In order to seek such a trend, the components disposed in the electronic device must be reduced in volume correspondingly, and the connectors used therein also must be reduced in volume without exception. For example, the USB connector has developed a mini USB connector, and the digital video signal transmission interface evolves from a digital video interface to a high definition multi-media interface having a smaller volume and a faster transmission speed.
现代电子产品的设计除了要功能多样外，在外观上的趋势是追求轻、薄、短、小，为了追求这样的趋势，电子产品内的各个零件也必须跟着将体积缩小，其所使用的电连接器当然也不例外，如通用串行连接埠推出迷你版的通用串行连接端口，而数字影音讯号的传输接口也由数字视觉接口推演到体积较小，传输速度更快的高速高解析多媒体接口。
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objective to evaluate dsa and percutaneous transluminal renal arterioplasty for the treatment of renovascular hypertension.methods 82 suspected patients with renovascular hypertension were given dsa examination.28 patients were treated by means of ptra while another 5 cases with unilateral kidney atrophy treated surgically.results 49 patients were normal,33 patients were abnormal,28 patients were treated by means of ptra.blood pressure had got to normal in 10 patients while in 13 patients bp dropped noticeably after ptra.the overall benefit rate was 82.1%.conclusion dsa and ptra are clinically effective for the treatment of renovascular hypertension.ptra is technically successful.
目的 评价经皮腔内肾动脉成形术治疗肾血管性高血压的价值。方法 82例全部行dsa检查，肾血管狭窄者行ptra术或外科手术，观察其治疗效果。结果 82例患者行肾动脉造影后血管正常者49例，异常者33例，其中单侧肾萎缩5例行外科手术（肾动脉搭桥1例），肾动脉狭窄28例行经皮腔内肾动脉成形术（血管内支架5例），术后10例血压降至正常或基本正常，13例血压得到改善，5例无效，总有效率达82.1%。结论 dsa检查和ptra术在诊断和治疗肾血管性高血压方面有明显的临床价值。高血压，肾血管性；数字减影血管造影术；经皮腔内肾动脉成形术
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MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available
MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可
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TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available
TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可
- 更多网络解释与数字行相关的网络解释 [注：此内容来源于网络，仅供参考]
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Show dialer：显示为DDR(数字数据接受器)设置的串行接口的一般诊断信息
Show cdp neighbors 显示CDP查找进程的结果 | Show dialer 显示为DDR(数字数据接受器)设置的串行接口的一般诊断信息 | Show flash 显示闪存的布局和内容信息
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Show dialer：显示为DDR(数字数据接收器)设置的串行接口的一般诊断信息
Show access-lists 显示当前所有的ACL的内容 6 | Show dialer 显示为DDR(数字数据接收器)设置的串行接口的一般诊断信息 12 | Show frame-relay lmi 显示关于本地管理接口(LMI)的统计信息 13
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Show dialer：显示为DDR(数字数据接受器)配置 的串行接口的一般诊断信息
Show cdp neighbors 显示CDP查找进程的结果 | Show dialer 显示为DDR(数字数据接受器)配置 的串行接口的一般诊断信息 | Show flash 显示闪存的布局和内容信息
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digitigrade：趾行类的
digitigrade 趾行动物 | digitigrade 趾行类的 | digitiserdigiverter 数字转换器
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linefeed：换行
其返回值则为相对应之底角的度数,以「弧度」为单位. 正切函数值 (number) 的算法为「对边除以邻边」. 0到 31 之间的数字与一般、非列印的 ASCII 码相同. 例如,Chr(10) 会返回换行(linefeed)字元.
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mobile phone：行動電話
而蓝芽技术应用之电子产品包括:个人数字助理(PDA)、行动电话(Mobile Phone)、无线电话(Cordless Phone)、笔记型计算机(Notebook)、打印机(Printer)、数字相机(Digital Cameras),局域网络(Network)等,可以将这些有线的产品变成无线.
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nixie tube：数字管
nip 核心初始化程序 | nixie tube 数字管 | nl 移行符号
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line number：行号
(5)除了用行号(line number)以外,还可以用"行标号"(line label). 行标号由1-40个字母或数字后加一个":"号组成. 例如下面程序最后一行开头的"a:"就是一个行标号. 它的作用是该行的标识,常用于转移语句的指向. 第三行中的"GOTO a"就是使流程转到END语句.
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numerical control system：数字控制系统
*动易网络--领先的内容管理系统(CMS)、网上商店系统(eShop)和企业*数字控制系统(Numerical Control System)发展史-数控系统-电气行[简介]数字控制系统(Numerical Control System)发展史2009/5/19/16:12 1946年诞生了世界上第一台电子计算机,
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serial port：串行端口
网络接口 串行端口(Serial Port) 3通道UART(包含IRDA通讯接口) CANBus接口 一个现场局域总线(CANBus)接口(选配) RIC实时时钟 具备后备锂电池 TFT24bit LCD控制器接口 最大支持800×600 640×480 320×240 TFTLCD A/D转换接口 10路10位 触摸屏接口 四线式 其它接口 IIC总线接口 JTAG调试接口 SPI总线接口 数字音频输入/输出接