并行传送

词组短语

parallel transfer

与并行传送相关的网络例句 [注：此内容来源于网络，仅供参考]

The three states are transformed via two-dimension liquid crystal element and polarizators, and ternary arithmetic operation and ternary logic al calculus completed directly in this way.

三值光计算机用相互垂直的两个线偏振光和零光强三个独立的光状态表示信息；用二维液晶器件和偏振器实现此三个状态间的转换；采用三进制算术运算；直接处理三值逻辑运算；拥有巨大的数据位数(容易超过10~4位)；具有光运算、光传送、电控制等结构特色，具有很强的空间、时间并行性。

Parallel data transmission : In paralleled data transmission ,bits are transmitted through separate lines simultaneously .

在并行的数据传输中，位通过独立线路同时被传送。

Be aimed at these problems, put forward a kind to convey for many times the collateral algorithm of reapportion data .

针对这些新问题，提出了一种多次传送重新分配数据的并行算法。

Additionally, they have developed a prober-based system, called Sidewinder, for testing devices in strip format that allows their customers to take advantage of the higher parallel test capability and uniform material handling provided with testing packaged devices in strip format.

此外，伊智还研发了基于探针台技术的机械手系统Sidewinder，实现了strip格式的器件测试，使其客户能在strip封装测试中高度利用并行测试能力和独特的材料传送技术。

An image acquisition system snapping three instantaneous images at the same time with a color image board has been designed, it can obtain homochromy laser spot images at difference orientation in ICF experiment.

设计和开发了利用单块彩色图象采集板实现三通道并行瞬态图象采集系统，利用它可同时测量ICF实验不同方位的激光焦斑单色图象，并将采集图象实时传送到数据处理中心。

Aiming at solving these problems, this paper proposed a parallel algorithm with multi-transmitting redistributed data.

针对这些问题，提出了一种多次传送重新分配数据的并行算法。

The address is transmitted to the memory through a set of parallel wires called an address bus. A 16-bit address bus can locate 64K(2^16) or 65536 memory locations. A 32-bit address bus can locate 4 Gigas(2^32) of different memory locations.

向存储器传送地址是经过一组为地址总线的并行导线进行的。16位地址总线可以确定64K （2的16次幂）即65536个存储位置。32位地址总线可以确定4G （2的32次幂）个不同的存储位置。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

The data from the sending station is carefully divided into four parallel streams, encoded, transmitted and detected in parallel, and then reassembled into one received bit stream.

从发送站送出的资料到被小心地分割成四个平行的串流，并行地编码、传送和侦测，随后被重组成一接收到的位元串流。

与并行传送相关的网络解释 [注：此内容来源于网络，仅供参考]

init：初始化

其数据线信号为DATA0~DATA7,控制线信号为"选通"(STROBE)、"初始化"(INIT)、"打印机输入选择"(SLCTIN)和"自动进纸"(AUTOFDXT). 其中,在SLCTIN信号为低电平时,表示使用并行接口向打印机传送数据信息;而当STROBE产生负脉冲信号进,

parallel transfer：并行传送

parallel to serial conversion 并-串变换,并串联变换 | parallel transfer 并行传送 | parallel tuned circuit 并联调谐电路

transfer,parallel：并行转移

transfer, block (方)块转移;字段传输;字组传输 | transfer, parallel 并行转移 | transfer, peripheral 外围传送;外围转移

strobe：选通

其数据线信号为DATA0~DATA7,控制线信号为"选通"(STROBE)、"初始化"(INIT)、"打印机输入选择"(SLCTIN)和"自动进纸"(AUTOFDXT). 其中,在SLCTIN信号为低电平时,表示使用并行接口向打印机传送数据信息;而当STROBE产生负脉冲信号进,