定时锁

词组短语

time lock

与定时锁相关的网络例句 [注：此内容来源于网络，仅供参考]

Your Blackberry will automatically lock itself when it is not in use, which helps to protect your data.

您的黑莓本身会自动锁定时，不使用，有助于保护您的数据。

Main technical data: AT89C51 monolithic machine: 4 K FPEROM procedure memory , 128 byte data memory, 2 16 timers 74 LS373 locks exist implement: The electrical level having three state the door outputing allows 8 D.

AT89C51单片机： 4K FPEROM程序存储器，128字节数据存储器，2个16位定时器 74LS373 锁存器：具有输出三态门的电平允许8D。

Fully Integrated Clock Recovery and Data Retiming Power Dissipation: 260mW with +3.3V Supply Clock Jitter Generation: 5mUIRMS Exceeds ANSI, ITU, and Bellcore SDH/SONET Jitter Specifications Differential Input Range: 50mVP-P to 1.6VP-P Single +3.3V Power Supply PLL Fast Track Mode Available Clock Output Can Be Disabled Input Data Rate: 2.488Gbps or 2.67Gbps Selectable Output Amplitude Tolerates 2000 Consecutive Identical Digits Loss-of-Lock Indicator Differential CML Data and Clock Outputs Operating Temperature Range:-40C to +85C

1第1页，本页显示记录1-5，共5条记录分1页显示完全集成的时钟恢复和数据重定时功耗：+3.3 V电源与时钟抖动产生：5mUIRMS超越美国ANSI，ITU和Bellcore实验室的SDH / SONET抖动规格差分输入范围：50mVP磷260mW至1.6VP - P的单+3.3 V供电锁相环快车道时钟输出模式下可用可以禁用输入数据速率：2.488Gbps或2.67Gbps可选输出振幅2000年连续容忍同位数丢失锁指示灯差分CML数据和时钟输出工作温度范围：-40℃至+85

When locked in phase and frequency, the output is high impedance and the voltage at that pin is determined by the low-pass filter capacitor.

当相位和频率锁定时，输出端为高阻态、那个脚的电压取决于低通滤波电容。

HonePhreak Software PocketSensor Automatic Keylock v1.0 S60v5 SymbianOS9.4 Retail-FoXPDA PocketSensor uses your phone's built-in proximity sensor to automatically lock the phone when it is put in a pocket.

ocketSensor使用手机内置的接近性传感器自动锁定时，装在口袋里挂上了电话。

The clock multiplier unit, which is based on phase-locked loops generates 2.5 GHz clock from external 156MHz reference clock to supply PISO and data retimer.

时钟倍频单元采用基于锁相环的结构，将外部输入的156 MHz时钟16倍频得到2.5 GHz内部时钟供并串转换单元和数据重定时单元使用。

His trademark is an amber holder and his proudest possession appears to be his cigarette case with built-in timer and lock.

他的&注册商标&是一个琥珀烟嘴，而他最引以为自豪的财产似乎就是他的烟盒——装有内插式定时器和锁。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

This board uses two chips, six channels A/D converter and phase locking synchronous technology for collecting three-phase voltage and current signals in timing and equal-time cycle sampling ways, and the gained data make more reasonable for power quality norm analysis.

并采用了两片六通道高速A/D转换器和运用了锁相同步技术，对三相电压和电流信号能进行定时采样和等间隔采样，这样得到的数据对于下一步电能质量指标进行分析更为合理。

与定时锁相关的网络解释 [注：此内容来源于网络，仅供参考]

time loan：定期贷款

time limit 时限 | time loan 定期贷款 | time lock 定时锁

time lock：定时锁

沥青拌和厂应装设定时锁(Time Lock)以控制拌和时整个循环之操作. 定时锁於粒料导入拌和机后,应即锁闭称重箱之闸门,直至完成拌和之循环并关闭拌和机之闸门时为止. 定时锁於整个乾拌期间应能锁闭沥青漏斗,并於整个乾拌及湿拌期间能锁闭拌和机之闸门.

time lock WESTBANK：定时锁

time line WESTBANK 时间线 | time lock WESTBANK 定时锁 | time of concentration WESTBANK 集中时间,集流时间

Dual custody with a three-movement S&G time lock：另外一把锁是三连动SG定时锁

The lock's a 1922 Moss Hamilton.|锁是1922摩斯.汉... | Dual custody with a three-movement S&G time lock,|另外一把锁是三连动SG定时锁 | another S&G mounted vertically down, whatever that means.|另外一个SG...

The vault has a time lock, pressure mounts, steel plates：金库装着定时锁,压力装置,钢板

They couldn't make heads or tails of it.|他们没任... | The vault has a time lock, pressure mounts, steel plates.|金库装着定时锁,压力装置,钢板 | - This guy didn't open a door. - Open a door?|-这家伙门都没...

Interlocks：联锁

硬件联锁(Interlocks)装置允许联机编码. MaverickKeyTM硬件编程ID,可用于数字版权管理(DRM)和设计知识产权的保护:看门狗(Watchdog)定时器. EP9302包含增强型和标准型的GPIO. 其中,16个增强型的GPIO可单独配置为输入、输出和带中断功能的输入引脚;

peripherals：外设

丰富的外设(Peripherals)DSP处理器往往是脱机独立工作,因此为与外设接口方便,往往设置了丰富的周边接口电路. 一般包含下列几种主要外设:时钟产生器(振荡器与锁相环PLL);定时器(Timer);软件可编程等待状态发生器,