全加器

词组短语

full adder

与全加器相关的网络例句 [注：此内容来源于网络，仅供参考]

At last, optical half /full adders based on single SOA and several optical bandpass filter are theoretically proposed.

最后从理论上提出了基于单个SOA和若干个并联的滤波器组合的全光半加器和全加器。

This is a use of embedded hardware-based high-level language to describe the All-Canadian program to meet the functions of the binary full adder.

详细说明：这是一个基于嵌入式的利用硬件高级描述语言编写的全加器程序，可以满足二进制全加的功能。

The course of logic operations of carry lookahead adder for binary number is introduced into optical computation. The carry lookahead by optical parallel processing is proposed.

将二进制数的先行进位全加器的逻辑操作引入到光计算中，提出了用光学并行处理方法实现先行进位全加器逻辑操作的建议。

In this paper, we propose a new method to implement full adder based on chaos computing. By setting different thresholds and judgment conditions, the full adder is implemented by using only one chaotic unit.

基于混沌计算的思想提出了实现全加器的新方法，通过设定不同的阀值及判断条件，使用一个混沌单元实现全加器。

This is a 4-bit full adder, a half-price with a make a full-adder, and then made four half adder.

详细说明：这是一个4位全加器，用一个1位半价做的一位全加，然后做成的四位半加。

The program is to achieve the n-bit full adder, first using the door with non-realization of a family - and finally realize the full n-bit adder.

该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。

Experiment include the operation of a half adder, full adder, plus / subtraction device, and the use of logic diagram VHDl descripti...

实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。

This is my ISP programming experiment in the preparation of an independent structural description of the four full-adder, through the four mapping of a full adder means four full-adder function, together with a digital display module will be full adder computing the results output to a digital display.

详细说明：这是我在ISP编程实验中独立编写的采用结构化描述的四位全加器，通过四次映射一位全加器的方式实现了四位全加器的功能，并附有数码显示模块，将全加器的运算结果输出到数码管显示。

As an example, in the design of a 4-bit ripple carry adder, the second and fourth full adders do not use output inverters for carry generation. one inverter delay is eliminated for every two full adders in the adder chain, and four transistors are reduced. Similarly, in complex designs like the multiplier, the output inverters for generating sum and carry can be used in alternative stages, thereby improving speed and reducing area.

例如，在4位行波进位加法器中，第2级和第4级的加法器不需要用输出反向器进行进位产生，因此，加法器链上的反向器延迟每两级全加器抵消一次，因此可以减少4个晶体管，类似的，在乘法器这样的复杂设计中，用于产生"和"以及"进位"的输出反向器可以用于其它方面，因此可以改善电路的速度和减小面积。

We proposed three brand new full adders which is low power and realized in Bootstrapped Pass Transistor Logic.

为了使得有全加器有较低的功率消耗，本论文提出三个全新的全加器电路，其电路架构是以Bootstrapped传输逻辑闸所实现的全加器电路。

与全加器相关的网络解释 [注：此内容来源于网络，仅供参考]

full adder：全加器

通常采用全加器(Full Adder)来完成相同权重的位相加. 采用一位全加器,那么Wallace树的每一层,就可以将部分积的向量数目按照3:2的比例缩减. 也可以采用2个全加器,来获得4:2的缩减比例. 本文中采用3:2计数器(全加器)来进行部分和缩减,

full adder：全加法器全加器

full adder 全加法器 | full adder 全加法器全加器 | full adder 全加器

full binary adder：二进制全加器,全二进制加法器

full bandwidth 全帯域幅 | full binary adder 二进制全加器,全二进制加法器 | full binary tree 满二叉树

FA Full Adder：全加器

F1-C Flash Chip Enable 字库片选 | FA Full Adder 全加器 | FA-DET-N 电池温度检测

latching full adder：闩锁全加器

latching electromagnet 闭锁电磁铁 | latching full adder 闩锁全加器 | latching relay 闭锁继电器

parallel full adder：平行全加器

平行FORTRAN语言 parallel FORTRAN,PFOR | 平行全加器 parallel full adder | 平行全减器 parallel full subtracter

parallel full adder：并行全加器

parallel four wire feeder 平行四线式馈线 | parallel full adder 并行全加器 | parallel gage 块规

gated full adder：闸控全加器

闸控正反器 gated FF | 闸控全加器 gated full adder | 闸控信息 gated information

serial full adder：串行全加器

serial format 串行格式 | serial full adder 串行全加器 | serial full subtractor 串行全减器

serial full adder：串列全加器

"串列流","serial flow" | "串列全加器","serial full adder" | "串列全减器","serial full subtracter"