允许输出

基本解释 (translations)

EO

与允许输出相关的网络例句 [注：此内容来源于网络，仅供参考]

The system breakdown voltage measurement and signal output two most voltage measurement part in the main circuit simulation, tie amplifier module, A / D conversion module, module; Sunplus microprocessor through data processing, in the range of allowable error voltage measurements show, and broadcast voice.

本系统分电压测量和信号产生输出两大部分，电压测量部分以模拟电路为主，配合放大模块、A/D转化模块、显示模块；通过凌阳单片机进行数据处理，在误差允许范围内显示测量电压值，并播报语音。

Wave Settings allow channel selection, amplification and more than 30 output audio formats.

波设置允许通道选择，扩增和30多个输出音频格式。

To handle this, iPhone OS automatically displays a control that allows users to pick an output audio route.

为了解决这一点，iPhone OS自动提供了一个控件，允许用户选择一个输出音频路线。

Allows setting output mp3 Frequency, bit width, compression, operation mode and frequency filters.

允许设置输出的MP3的频率， Bit宽度，压缩，运作模式和频率过滤器。

The new features include the distinguishable ground fault LED, true input to output mapping, a power supply expansion board, and a larger chassis on the PS-8. The units can be used in a split mode operation, allowing the independent operation of the two inputs to any of the outputs.

PS-6和PS-8具备了新的特征，包括可识别的接地故障LED、输入与输出图示、电源扩展板和PS-8大底盘等装置，各装置可在分割模式下运行，允许相互独立的两个输入和任何输出同时工作。

Bibble uses an efficient system of work queues, print queues and batch queues that allow you toquickly process images based on custom defined settings that include output format, output folder,quality and various other options.

Bibble 使用一个高效的工作序列系统，打印序列和允许你基于定制的包括输出格式，输出文件夹，输出品质和各种不同的其他选项在内的预定义设置来进行快速地处理的批量序列。

Fourth, it conducts the formula deduction, analysis and numerical calculations of the noncollinear quasi-phase matching gains and the output parametric spectrum, which leads to the conclusions that under the same circumstances, the gains of noncollinear interaction will be much less than those of the collinear interaction, and consequently the noncollinear interaction possesses the larger acceptance bandwidths than that of the collinear interaction.

对非共线准相位匹配的增益和输出参量光的允许波长进行了公式推导、分析和计算，得到了允许信号光波长的精确公式和关系曲线。

The traditional parallel theory without control interconnections has been adopted commonly in the parallel inverter system. There is a deviation between the steady output frequency and the instruction of this system controlled by the above scheme,and the heavier the load is, the droopier the frequency will be. When the error is out of the permitted range, the system can not be operated normally.

逆变电源无线并联系统常采用传统无线并联理论，即电压-频率下垂理论控制，采用此方案控制的并联系统，其稳态输出电压频率与指令值有偏差，且所带负载越重，稳态输出频率下降越多，当偏差超出允许范围时就会对所带负载造成影响，使其不能正常工作。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

与允许输出相关的网络解释 [注：此内容来源于网络，仅供参考]

Asynchronous Transfer Mode：异步转移模式

电接口类型 输出口AIS比特率(ppm)指标要求 输出口AIS比特率(ppm)典型值电接口类型 输入允许频偏(ppm)指标要求 输入允许频偏(ppm)典型值时钟接口 输出抖动(UIpp)指标要求 输出抖动(UIpp)典型值ATM 异步转移模式(Asynchronous Transfer Mode)BMS 计费管理系

D CTS：允许发送 输出

4 C RTS 请求发送 输入 | 5 D CTS 允许发送 输出 | 6 E DSR 数据设备准备好 输出

D CTS：允许发送 输入

4 C RTS 请求发送 输出 | 5 D CTS 允许发送 输入 | 6 E DSR 数据设备准备好 输入

directory replication：目录复制

5、设置目录复制输出所使用的根目录 目录复制(Directory Replication)是WINDOWS XP支持的一种功能强大的服务,它允许在本地缓存共享目录的文件. 目录复制服务是由大量的注册表条目控制的,包括ExportPath. ExportPath列出了允许接收目录复制输出的服务器列表.

Homepage Excerpts：允许在首页的第一页显示全文输出,而在第二页之后显示文章的摘要输出

Google Analyticator - 在所有页面添加Google Analytics统计代码. | Homepage Excerpts - 允许在首页的第一页显示全文输出,而在第二页之后显示文章的摘要输出. | In Series Plugin - 制作一系列的相关文章.

OEA OutputEnable：允许输出,输出打开

ODR OutputDefinitionRegister 输出定义寄存器 | OEA OutputEnable 允许输出,输出打开 | OMS OutputMultiplexSynchronizer 输出多工同步器

OEA ObjectExtensiveArchitecture：对象广延体系结构

OE OutputEnable 允许输出,输出打开 | OEA ObjectExtensiveArchitecture 对象广延体系结构 | OEAP OperationalErrorAnalysisProgram 操作错误分析程序

Alarm Output：报警输出

4、按up arrow 或down arrow 键生效(ON)或消(OFF)安全锁●动态时间划分(DTD)多路处理允许摄像机的录像时间以画面移动●独立的主(MAIN)和(CALL)监视器输出允许同时观看多摄像机括报警保持输入(Alarm Hold Input)和报警输出(Alarm Output)报警保持输入(Al

DOUT：数据输出

MAX16825提供4线串口,3位移位寄存器以及3位透明锁存器. 串口允许微控制器通过四个输入(DIN、CLK、LE以及低电平有效的OE)和一个数据输出(DOUT)配置输出通道. DOUT允许多个驱动器级联实现协同工作.

OMS OutputMultiplexSynchronizer：输出多工同步器

OEA OutputEnable 允许输出,输出打开 | OMS OutputMultiplexSynchronizer 输出多工同步器 | OP OutputPower 输出功率