中断屏蔽

基本解释 (translations)

IM  ·  unmasking

与中断屏蔽相关的网络例句 [注：此内容来源于网络，仅供参考]

Note that only data-inthat are registered prior to the t DPL period are written to the internal array, and any subsequent data-in should be masked with DM.

写操作会被预充电指令中断，但是在 tDPL 时间之前就被锁存的数据会被写入存储器，之后的数据就会被 DM 信号屏蔽。

In order to resolve the conflict in this equipment, we can operate in accordance with the following steps to set up: First of all, in the settings window will COM2 shielding, and forced to interrupt the network card is set to 3; if they are PCI interface card and the graphics are in conflict, We can not be allocated to the graphics card IRQ solution is to CMOS in a Assign IRQ for VGA is set to "Disable".

为了解决这种设备的冲突，我们可以按照如下操作步骤来进行设置：首先在设置窗口中将COM2屏蔽，并强行将网卡中断设为3；如果遇到PCI接口的网卡和显卡发生冲突时，我们可以采用不分配IRQ给显示卡的办法来解决，就是将CMOS中的 Assign IRQ for VGA 一项设置为"Disable"。

It is a global masking process for any interrupt of level higher than n.

对于比n更高的任何中断级来说，这是一个总的屏蔽处理。

TL084MJ Pinout: 3.3V Operation with 5V Tolerant Buffers ACPI 1.1, PC99/PC2001 Compliant LPC Interface with Clock Run Support Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems 15 Direct IRQs Four 8-Bit DMA Channels ACPI SCI Interface nSMI Shadowed write only registers Internal 64K Flash ROM Programmed From Direct Parallel Interface, 8051, or LPC Host 2k-Byte Lockable Boot Block Can be Programmed Without 8051 Intervention Three Power Planes Low Standby Current in Sleep Mode Intelligent Auto Power Management for Super I/O ACPI Embedded Controller Interface Configuration Register Set Compatible with ISA Plug-and-Play Standard (Version 1.0a) High-Performance Embedded 8051 Keyboard and System Controller Provides System Power Management System Watch Dog Timer 8042 Style Host Interface Supports Interrupt and Polling Access 256 Bytes Data RAM On-Chip Memory-Mapped Control Registers Access to RTC and CMOS Registers Up to 16x8 Keyboard Scan Matrix Two 16 Bit Timer/Counters Integrated Full-Duplex Serial Port Interface Eleven 8051 Interrupt Sources Thirty-Two 8-Bit, Host/8051 Mailbox Registers Thirty-six Maskable Hardware Wake-Up Events Fast GATEA20

TL084MJ引脚说明： 3.3V工作电压为5V容错缓冲器的ACPI 1.1，PC99/PC2001符合LPC接口与时钟运行支持-兼容串行接口与串行的IRQ IRQ的支持PCI系统- 15直接的IRQ - 4个8位DMA通道- ACPI的SCI接口- nSMI -阴影只写寄存器内部的64K的Flash ROM -直接从程序并行接口，8051，还是LPC主机-的2K字节可锁定引导块-可在不干预程序8051三力飞机-低待机电流在休眠模式-智能型自动电源管理的超级I / O的ACPI嵌入式控制器接口配置寄存器设置兼容的ISA拆开的播放标准（版本1.0a）高性能嵌入式8051键盘和系统控制器-提供系统电源管理-系统监视狗定时器- 8042型主机接口-支持中断和轮询访问- 256字节数据RAM -片上存储器映射控制寄存器-获取实时时钟和CMOS寄存器-最多16x8矩阵键盘扫描- 2个16位定时器/计数器-综合全双工串行接口- 11个中断源8051 - 32个8位，Host/8051邮箱寄存器- 36个可屏蔽硬件唤醒事件-快速GATEA20

In interrupts, the setting of a mask bit to0 is called disabling an input/ output processing.

在中断中，置一个屏蔽位为0叫作输入输出处理禁止。

The dspic30f has a vectored exception scheme with up to 8 sources of non-maskable traps and 54 interrupt sources.

dipic30f有一个矢量异常系统，带有8个不可屏蔽的traps源和54个中断源

Pinout: C High-performance 32-bit RISC Architecture C High-density 16-bit Instruction Set C Leader in MIPS/Watt C Little-endian C Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM C 32-bit Data Bus C Single-clock Cycle Access Fully Programmable External Bus Interface C Maximum External Address Space of 64M Bytes C Up to Eight Chip Selects C Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller C Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter C Three External Clock Inputs C Two Multi-purpose I/O Pins per Channel Two USARTs C Two Dedicated Peripheral Data Controller Channels per USART Programmable Watchdog Timer Advanced Power-saving Features C CPU and Peripheral Can be Deactivated Individually Fully Static Operation: C 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package

M5L8253P-5引脚说明： C型高性能32位RISC架构C高密度以MIPS /瓦C小端C十六位指令集C领袖嵌入式冰8 - 16 -位和32位的读写支持256K的片上SRAM的 32位数据总线C单时钟周期存取字节完全可编程的外部总线接口C最大的外部地址空间的64M字节多达8个C芯片选择C软件可编程8位外部数据总线8级优先级，独立可屏蔽，向量中断控制器C四外部中断，其中包括一个高优先级，低延迟中断要求32个可编程I / O口线三通道16位定时器/计数器C三个外部时钟输入C两多用途I / O引脚每通道2个通用同步C两专用外设数据控制器通道每个USART可编程看门狗定时器先进的节能特性 CPU和外设可停用独立全静态工作中：C 0 Hz至75 MHz的频率范围内的VDDCORE = 1.8，85℃2.7V到3.6VI / O的操作1.65V到1.95V范围核心工作电压范围在- 40C至+85 C温度范围内使用的100引脚TQFP封装

与中断屏蔽相关的网络解释 [注：此内容来源于网络，仅供参考]

Interrupt Disable：中断屏蔽

停止 HALT | 中断屏蔽 Interrupt disable | 中断允许 Interrupt enable

interrupt priority：中断优先权

interrupt mask,中断屏蔽 | interrupt priority,中断优先权 | interrupt priority system,中断优先权系统

interrupt priority：中断优先

interrupt mask 中断屏蔽 | interrupt priority 中断优先 | interrupt request 中断请求

interrupt mask：中断屏蔽

(a)实施中断屏蔽(Interrupt Mask)等互斥处理,禁止库函数执行过程中的中断要求. (b)不在中断处理程序中处理对端口的访问,而是使用实时操作系统等把对该端口的访问改为单线程,以此防止多个模块间的资源访问竞争. 不过,

interrupt mask：隐中断字,中断屏蔽

interrupt lockout 封锁中断 | interrupt mask 隐中断字,中断屏蔽 | interrupt mask bit 中断屏蔽位

interrupt mask bit：中断屏蔽位

interrupt mask 隐中断字,中断屏蔽 | interrupt mask bit 中断屏蔽位 | interrupt mask flag 中断屏蔽标志

CLI Clear Interrupt Mask Bit：(中断屏蔽位I 清零)

CLC Clear Carry Bit(进位位C 清零) ................... | CLI Clear Interrupt Mask Bit(中断屏蔽位I 清零) .................................................. 203 | CMP Compare Accumulator with Memory(A 与M...

SEI Set Interrupt Mask Bit：(中断屏蔽位置位)

SBC Subtract with Carry(带借位减法) .......... | SEC Set Carry Bit(进位位置位) ................. | SEI Set Interrupt Mask Bit(中断屏蔽位置位) .......................................................... 227

unmask state：无屏蔽状态

无屏蔽 unmask | 无屏蔽状态 unmask state | 无屏蔽(处理),中断屏蔽(处理) unmasking

Unmasking：无屏蔽(处理),中断屏蔽(处理)

无屏蔽状态 unmask state | 无屏蔽(处理),中断屏蔽(处理) unmasking | 未匹配,失配,不配对 unmatch