stripline

stripline的基本解释

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带状线

与stripline相关的网络例句 [注：此内容来源于网络，仅供参考]

The asymmetric stripline is widely used in LTCC microwave integrated circuit system. Different kinds of discontinuity are often encountered in the circuit design, such as open circuits, steps, right-angle bends, T-junctions and so on. This paper successfully transplantes the equivalent circuit model of microstrip line discontinuity to the asymmetric stripline so as to deal with T-junction discontinuity and the branch-line coupler constructed by parts with various discontinuity. Compared with numerical results, the average error of S parameters is less than 2%.

偏心带状线广泛应用于LTCC微波集成电路系统中，其电路设计过程中也经常会遇到诸如开路端、阶梯、直角拐角及T型接头等各种不连续性问题；该文成功地将原有的微带线不连续性等效电路模型移植到偏心带状线上，从而分析了其T型接头不连续性和由其不连续性部分组成的电路组件分支线耦合器；与数值计算结果相比，其S参量的平均误差小于2%。

A multiplayer chip LC resonator was fabricated using planar inductor and parallel plate capacitor. Because lumped inductor has small Q value and there is stray parameter effect in high permittivity substrate, the Q value of chip LC resonator is not high. Resonators based on λ/4 stripline with end short circuited were designed and fabricated. Input and output pads, coupled to the stripline using gap-coupling capacitor, are in the same layer with the center conductive strip. This new structure is very convenient for manufacturing in comparison with the conventional structure.

采用间隙电容耦合结构实现的谐振频率为1.8GHz四分之一波长终端短路带状线单端口谐振器的Q值最大值为225，谐振频率为1GHz双端口谐振器的Q值为83，谐振频率和Q值与耦合间隙、带状线的厚度和耦合引线长度有关；二分之一波长带状线谐振器的Q值和四分之一波长相比较尺寸较大，由于导电带较长，造成金属的损耗增加，从而导致谐振器的Q值较低；带状线结构的谐振器频率调节困难，本文提出了改变接地端的宽度实现谐振频率的微调方法，可实现频率调节量约1.5%。

Also, by using a novel offset architecture, as opposed to completely overlapped architecture, for the differential transmission pair, a 33% reduction of thickness is achieved in the design of a miniaturized common-mode filter with multi-layer LTCC technology. In view of increasing need of high-speed clock and data circuits to control their skew problems, a design of LTCC delay line is then conducted. To improve the waveform distortion associated with the microstrip/stripline-type meander delay line, a miniaturized high-frequency 3-D delay line with grounded guard traces is introduced. By means of 3-D structure, the 233 ps delay time, which requires extra board space amounting to a factor of 2.34 by stripline type meander delay line, can be shrunk into an EIA 1206 form factor.

为因应高速时脉及高速线路的不断发展，用於控制讯号、时脉同步的延迟线路需求日益增加，接著讨论的题目便是应用低温共烧陶瓷制程技术设计多层的延迟线路元件，为了改善在微带线/带线型折线式延迟线路波形失真的问题，论文中提出以接地的防护线来设计小型化的三维多层延迟线路元件，比较应用带线型折线式延迟线路和应用三维架构设计的延迟线路元件，同样提供233 ps的延迟时间，多层架构设计之延迟线路可缩小至EIA 1206 的尺寸，省下2.34倍的电路板面积。

与stripline相关的网络解释 [注：此内容来源于网络，仅供参考]

stray capacitance：散杂电容

静态场 static field | 散杂电容 stray capacitance | 带状线 stripline

stripline circulator：带状线循环器带状线衰减器

stripline antenna 带状线天线 | stripline circulator 带状线循环器带状线衰减器 | stripline filter 带状线滤波器

stripline circulator：带状线回圈器带状线衰减器

strip transistor 带型电晶体 | stripline circulator 带状线回圈器带状线衰减器 | stripline filter 带状线滤波器