processor [prə'sesə]

processor的基本解释

n.

处理机, 处理器

与processor相关的网络例句 [注：此内容来源于网络，仅供参考]

The co-channel interference rejection filter for outputting a second input signal by removing co-channel interference from a first input signal; a first post processor for removing interference other than co-channel interference from the second input signal; a second post processor for removing interference other than co-channel interference from the first input signal; and a selection controller for selecting the output of the post processor which has less error by comparing the output of the first post processor with the output of the second post processor.

一种共道干扰消除器及其方法，其中抗共道干扰滤波器从第一输入信号中除去共道干扰并输出第二输入信号，第一后置处理器除去第二输入信号中的非共道干扰，第二后置处理器除去第一输入信号中的非共道干扰，选择控制器比较第一后置处理器和第二后置处理器的输出，从中选择误差较小的后置处理器输出。

Based on a lot of experiment results, a conclusion is drawn: comparing with other factors, the performance of branch handling strategy is the key limits of processor to exploit the instruction level parallelism existed in nonscientific code, cache miss have severe effect on superscalar processor's performance when it runs scientific code. Second, in order to reduce the branch penalty and improve the performance of superscalar processor, a new branch handling strategy—a classification based hierarchical branch handling strategy, CHBHS is proposed. It first expands the traditional processor architecture to support multiple condition code, conditional execution and Mbranch instruction, as a result, compiler can reduce the number of static conditional branch when the code is generated. Then, CHBHS tries to use the best suitable mechanism to deal with different branch base on their different behavior. CHBHS can predict the target address of unconditional branch, subroutine call and conditional branch by buffering their target address in branch target buffer, a newly proposed high efficient return address stack is used to reduce the penalty of subroutine return instruction, a new Counter Register Stack is also proposed to reduce the penalty of loop-closing branch to zero, and dynamic branch predictor is incorporate with branch target buffer to predict the outcome of conditional branch.

基于上述结论，为了尽量消除转移指令对处理器开发指令级并行性能力的影响，进一步提高处理器性能，在详尽分析目前已存在的转移处理策略的特点与局限性的基础上，首次提出了一种新的转移处理策略即基于分类的层次转移处理策略CHBHS(Classification Based Hierarchical Branch Handling Strategy)，它首先通过扩展传统的体系结构，支持多条件码、条件式执行及多分支转移技术，以使编译程序在进行代码生成时可尽量少生成条件转移指令，从而减少静态条件转移指令的数目；其次，基于不同的转移指令的行为不同这一事实，提出了对不同的转移指令采用不同的机制进行处理的思想，即对无条件转移指令和函数调用指令以及条件转移指令的目标地址，采用转移目标缓冲器来预测，对于函数返回指令，采用所提出一种的高效返回地址栈来预测其目标地址，对于大多数循环控制转移指令，采用所提出的Counter Register Stack来将其所可能带来的损失减少为0，对于其他的条件转移指令采用动态预测机制来预测其方向。

Each user is a Field-bus control node.SCM MCS-51 is used as its main processor,and Neuron CMOS as its assistant processor.The two processors cooperate with each other.the main processor sam pling and controlling,and the assistant processor taking chang of communication.

把整个系统作为一个LON网络，每个住户作为LON网络的一个现场控制节点并以MCS-51单片为主处理器，Neuron芯片为从处理器两处理器协同工作；主处理器采样控制，从处理器负责通信。

与processor相关的网络解释 [注：此内容来源于网络，仅供参考]

processor：处理器

当龙芯花钱使用MIPS指令集开发的CPU占据相当大的市场份额后,不仅别的国家就会花钱使用龙芯的CPU芯片技术, 而且以MIPS指令集开发的龙芯CPU还可能冲击Intel1的X86指令集体系的CPU市场. 二、 以"处理器"(processor)为关键词在摘要Abstract中查询,得到57项专利.

processor：处理机

虽然是笔误, 但个人认为看完题目就可以知道问题重点是在询问单步执行旗标, TF (trap flag,陷阱旗标),用於单步追踪除错时,所以也称为追踪旗标(trace flag), 而不是区分微处理机(Microprocessor)与处理机(Processor)的旗标命名差别.

processor：加工者

如果当前的Leader线程检测到事件源中的一个事件,它会做两件事情:首先,它把一个Follower线程提升为一个新的Leader,然后它自己将变为一个加工者(processor)线程将事件分离并分派给指定的事件处理程序,事件处理程序运行在接收事件的线程中.

processor：处理者

正当这种事务处理者(processor)的影响和工程师的观念取代独立农场主的职能时,大制造商和销售工程师也在注视着市场系统这个小商人的命根. 现在,农场里和城市中的老式中产阶级正在阻挡着由技术专家和有效率的专业人士所代表的前行之轮.

processor：abbr. proc; 处理器