ports

ports的基本解释

-

[变形] port的第三人称单数

vi.

左转舵

n.

港口, 埠, 舱门, 避风港, 左舷, 炮眼, 意义

vt.

左转舵, 持(枪)

与ports相关的网络例句 [注：此内容来源于网络，仅供参考]

Of all the above, the constructor is used mainly to generate and set ports and parameters; Ports acting as the channel for data transmission among actors are defined as input ports, output ports or input/output ports. They are also set as single port or multiple ports; parameters are used to allocate actors. In the document, it may be set as an default value or as vacancy to define the data type of parameters, while the specific function to be implemented by the actor shall be defined by public method. Within the actor, the implementing sequence and functions of the method is generally seen as follows

其中构造函数主要用于创建和设置端口和参数；端口作为角色间数据传输通道，它被定义为输入端口，输出端口或输入/输出端口，并被设置为单端口或多端口；参数用于配置角色，它在文件中可设有默认值或为空，并定义参数的数据类型；而角色执行的具体功能由公有方法定义，角色内这此方法的执行顺序及功能一般如下

Based on a study of the influencing factors to ports throughputs, this paper analyzes the relationship between the factors and the throughputs, used the linear regression prediction models to forecast the throughput of nationwide, so the coastal ports can be achieved, then based on the relations of the whole and the part, we can got the throughput of Tianjin, Dalian and Qingdao port; in addition, this text choused to use three models of trend extrapolation model , and made the detailed introduction to these three model"s principles, e.g. the Logistic growth curve Model, grey system model and exponential smoothing model to Predict the Tianjin, Dalian and Qingdao ports" throughput, compared these results, got three ports throughput in 2007 and 2010 years.

并在此基础上，通过整体与局部的关系，再预测环渤海港口群中的天津、大连和青岛港的货物及集装箱吞吐量；另外，本文还选用了趋势外推法中的三个预测模型，并对这三个模型原理作了详细的介绍，然后引用&逻辑斯谛生长函数&模型预测了天津、大连和青岛港集装箱吞吐量；用指数平滑和灰色系统模型预测这三港的货物及集装箱吞吐量；最后，通过分析比较这些模型的预测结果，得出三港在2007和2010年货物及集装箱吞吐量预测结果。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

与ports相关的网络解释 [注：此内容来源于网络，仅供参考]

ports：端口

如同类(Class)可能有接口一样,端口(Ports)能同样的有接口. 这种端口(Ports)都表示当类(Class)的实例产生后分别可设定位置的类. 图一是一有端口(Ports)和接口的活动类(Active Class)的例子. 通常,这种类对软件和硬件的建模是非常有用的.

ports：宝姿

在职期间,成功设计了"宝姿"(PORTS)品牌2007秋冬季节男装的梭织产品,包括外套(夹克、大衣、休闲西装)、裤子、衬衫等. 2006.10至今 宝姿服饰(厦门)有限公司,宝马服装服饰中国总代理,担任服装设计师,主要负责男、女装的针、梭织产品的设计和开发.

ports：(加拿大)宝姿

以在国内进行成功品牌经营的加拿大"宝姿"(Ports)服装企业为例,其设计师队伍每季会设计出一千多件服装式样供营销部门选择,服装的批量一般只有200-500件左右,与国内企业动辙生产上万件的批量形成巨大的反差.

ports：港口

油轮 Oil tankers | 港口 Ports | 潜水艇 Submarines

well-known ports：端口

(1)知名端口(Well Known Ports):从0到1023,它们紧密绑定(binding)于一些服务. 通常这些端口的通讯明确表明了某种服务的协议. 例如:80端口实际上总是HTTP通讯. 下面列举日常中最常用的知名端口 (Well Known Ports)和对应的服务