delay line memory

delay line memory的基本解释

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延迟线存储器

与delay line memory相关的网络例句 [注：此内容来源于网络，仅供参考]

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The boundary of analytical model and statistical model is clearly divided in this performance model, and evaluation accuracy is improved. Secondly, based on embedded SRAM performance hybrid model, this article adopts bionics algorithm-ant algorithm to optimize hierarchical embedded SRAM structure. This method which adjusts memory system structure improves memory system performance. Finally, considering the factors such as memory cell area, power, delay and reliability, this article establishes static 6-T memory cell area, power, delay and static noise margin equations, analyzes 6-T memory cell device dimension constraints under "read upset" and "write upset", then proposes a method to enhance embedded SRAM performance by optimizing 6-T memory cell size. In order to realize embedded SRAM design and verify proposed optimization methods, this article takes the Garfield202 system chip as the platform, which embeds A720T processor and 20KB Scratch-Pad memory.

首先针对嵌入式SRAM结构，采用多元线性回归方法分析SRAM宏单元性能指标，采用解析方法分析控制电路延时，结合以上这两种方法建立嵌入式SRAM性能混合模型，该模型清晰划分两种建模方法的各自适用范围，提高了模型精度；其次以该混合模型为基础建立存储体性能目标函数，采用仿生优化算法—蚂蚁算法优化嵌入式SRAM结构，使之达到最优设计；最后综合考虑面积、功耗、速度以及可靠性等因素，建立静态6-T存储单元面积、功耗、延时以及静态噪声容限方程，分析了&读破坏&和&写破坏&的晶体管尺寸约束，优化了6-T存储单元尺寸，提高了嵌入式SRAM性能。

Also, by using a novel offset architecture, as opposed to completely overlapped architecture, for the differential transmission pair, a 33% reduction of thickness is achieved in the design of a miniaturized common-mode filter with multi-layer LTCC technology. In view of increasing need of high-speed clock and data circuits to control their skew problems, a design of LTCC delay line is then conducted. To improve the waveform distortion associated with the microstrip/stripline-type meander delay line, a miniaturized high-frequency 3-D delay line with grounded guard traces is introduced. By means of 3-D structure, the 233 ps delay time, which requires extra board space amounting to a factor of 2.34 by stripline type meander delay line, can be shrunk into an EIA 1206 form factor.

为因应高速时脉及高速线路的不断发展，用於控制讯号、时脉同步的延迟线路需求日益增加，接著讨论的题目便是应用低温共烧陶瓷制程技术设计多层的延迟线路元件，为了改善在微带线/带线型折线式延迟线路波形失真的问题，论文中提出以接地的防护线来设计小型化的三维多层延迟线路元件，比较应用带线型折线式延迟线路和应用三维架构设计的延迟线路元件，同样提供233 ps的延迟时间，多层架构设计之延迟线路可缩小至EIA 1206 的尺寸，省下2.34倍的电路板面积。

与delay line memory相关的网络解释 [注：此内容来源于网络，仅供参考]

delay line store：延遲線儲存

延遲線儲存器,延遲線儲存 delay line storage | 延遲線儲存 delay line store | 延遲線合成器 delay line synthesizer,DLS

控制延迟信号超过Ducker极限值时,对该延迟信号施加的衰减电平：Delay Atten

Delay Duck Thresh 延迟极限值控制 | Delay Atten 控制延迟信号超过Ducker极限值时,对该延迟信号施加的衰减电平 | Delay Level 延迟输出控制

delay-line inflector：延迟线偏转器

delay-line helix 慢波螺线 | delay-line inflector 延迟线偏转器 | delay-pulse generator 延迟脉冲发生器