SRAM

SRAM的基本解释

abbr.

Short Range Attack Missile 短程攻击导弹, 静态存储器

n.

static random access memory 静态存储器

与SRAM相关的网络例句 [注：此内容来源于网络，仅供参考]

It is because the spending of area and power of the SRAM memory cell takes a lot of percentage of the whole macro modules'. Using the α exponent MOSFET model to result the word line、bit line power model and delay model, together with the area model and analysis of the read/write reliability, we bring out a method to optimize the memory cell and evaluate the performance of the result.

特别对占模块面积和功耗绝大部分比例的SRAM存储单元做了细致的设计和仿真实验，通过采用α指数MOSFET模型推导出SRAM的字线、位线功耗模型和延迟模型，并配合存储单元的面积模型和读写可靠性分析，提出了一种优化存储体单元结构的方法，并对优化前后的性能进行了评估。

At last, based on characteristic of read data operation from SRAM, a precharge circuit using charge-recycling has been employed, and lower down the dissipation durig precharge.

最后，根据本文设计的SRAM读出数据没有使用读出放大器的特点，设计了电荷再分配的预充电路，使得在SRAM预充电时的功耗明显减小。

The boundary of analytical model and statistical model is clearly divided in this performance model, and evaluation accuracy is improved. Secondly, based on embedded SRAM performance hybrid model, this article adopts bionics algorithm-ant algorithm to optimize hierarchical embedded SRAM structure. This method which adjusts memory system structure improves memory system performance. Finally, considering the factors such as memory cell area, power, delay and reliability, this article establishes static 6-T memory cell area, power, delay and static noise margin equations, analyzes 6-T memory cell device dimension constraints under "read upset" and "write upset", then proposes a method to enhance embedded SRAM performance by optimizing 6-T memory cell size. In order to realize embedded SRAM design and verify proposed optimization methods, this article takes the Garfield202 system chip as the platform, which embeds A720T processor and 20KB Scratch-Pad memory.

首先针对嵌入式SRAM结构，采用多元线性回归方法分析SRAM宏单元性能指标，采用解析方法分析控制电路延时，结合以上这两种方法建立嵌入式SRAM性能混合模型，该模型清晰划分两种建模方法的各自适用范围，提高了模型精度；其次以该混合模型为基础建立存储体性能目标函数，采用仿生优化算法—蚂蚁算法优化嵌入式SRAM结构，使之达到最优设计；最后综合考虑面积、功耗、速度以及可靠性等因素，建立静态6-T存储单元面积、功耗、延时以及静态噪声容限方程，分析了&读破坏&和&写破坏&的晶体管尺寸约束，优化了6-T存储单元尺寸，提高了嵌入式SRAM性能。

与SRAM相关的网络解释 [注：此内容来源于网络，仅供参考]

AVID ULTIMATE：车刹

变速杆 SRAM TRIGGER X.0 | 车刹 AVID ULTIMATE | 后变 SRAM X.0

static RAM, SRAM：静态随机存储器

动态随机存储器 dynamic RAM, DRAM | 静态随机存储器 static RAM, SRAM | 静态存储器 static memory

SHIFTERS SRAM：指拨

指拨 SHIFTERS SRAM 5.0 | 前拨 FRONT DERAILEUR DEORE | 后拨 REAR DERAILEUR X5