RAM cache

与RAM cache相关的网络例句 [注：此内容来源于网络，仅供参考]

According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory.

根据一个实施例，数据处理系统中一致性管理的方法包括：在处于独占所有权一致性状态的较高级别高速缓存存储器中保存高速缓存线，以及其后从较高级别高速缓存存储器移除高速缓存线，并且从较高级别高速缓存存储器发送对高速缓存线的掷出请求到较低级别高速缓存存储器。

First, the effects of magnetic RAM relaxation time and the rise-time of incident pulse signal on reflection signal are discussed, the relationship between the rise-time of incident pulse and relaxation time based on the energy of reflection signal is revealed. Then, the effects of magnetic hysteric, susceptibilities and saturation upon reflection signal are analyzed, the results reveal the reflection of RAM target and UWB signal design. In the meantime, dielectric relaxation time effect about dielectric RAM target is analyzed simply, and the effects of relaxation time and the width of incident pulse upon reflection signal are probed. Finally, a few RAM targets are measured in the chamber using the impulse radar experiment system which is developed by the team of anti-stealth impulse radar on Department of Electrical Engineering, National University of Defense Technology. The experimental results show the similarity of the rule of echos with the theory. From the compared results of different tagets, we concluded, compared with 15% wideband sinusoidal signal, the impulse signal has increased 10～12dB energy from the same loaded RAM target; this, in turn, shows the nonlinear effects of RAM to the echoes, and the potentiality of the impulse signal to RAM targets.

首先分析了磁性RAM的弛豫时间及入射脉冲信号的上升时间对反射信号的影响，从反射信号能量角度出发，给出了入射脉冲上升时间与弛豫时间的关系；接着分析了磁性RAM的磁滞特性、磁化率及磁化强度对反射信号的影响，给出了RAM目标辐射和有关UWB信号设计的一般性结论；其次，对介电RAM的弛豫时间效应作了简单的分析，探讨了介电弛豫时间及入射脉冲宽度对反射信号的影响；最后利用国防科技大学电子技术系&反隐身冲激雷达技术研究组&研制的冲激雷达实验系统，在微波暗室中对几种不同的RAM目标进行了测量，结果表明：其反射波形的基本规律与上述理论分析相一致；从各种不同目标回波的能量对比结果得出，涂覆RAM目标对冲激信号的吸收比15％带宽的正弦信号要小10～12dB，证实了RAM的非线性效应对回波的影响，也证实了冲激信号反隐身的潜力。

The first level cache is split caches : instruction cache and data cache, each of which is single-cycle cache with direct-mapped organization. The second level cache is a hybrid and multicycle cache with two-way skewed-associative organization.

NRS4000是一个32位的嵌入式RISC产品，时钟频率为20MHz，采用5级流水技术，实现了面向寄存器的指令集（共128条指令），支持了寄存器窗口切换和基于优先级的中断、故障、跟踪、通信等功能，是一个完整的微处理器系统。

与RAM cache相关的网络解释 [注：此内容来源于网络，仅供参考]

RAM Cache：内存缓存

如果内存较小(32M以下),内存缓存(RAM CACHE)以较小为好,通常采用OPERA的默认值(500K)即可,如果内存较大(64M以上),且你经常在同一个网站浏览,适当增大内存缓存,将明显改善浏览速度,但最大不宜超过5MB.

RAM Cache：随机高速缓冲器

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RAM Cache：随机高速缓存器

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RAM Cache：随机存取记忆体快取

"随机存取记忆体存取时间","RAM access time" | "随机存取记忆体快取","RAM cache" | "随机存取记忆磁碟","RAM disk"

R RAM cache：随机高速缓冲器

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